Course overview
Introduction to fabrication processes, design rules (revisited); Transistor models (revisited from third year electronics); Layout issues; ASIC design flow; VLSI design methodology and leaf cell design; Performance estimation of CMOS complex gates and interconnected modules using logical effort; Interconnect issues; Clock distribution; Design margin, reliability and scaling; Static and dynamic CMOS logic families and adders design; Memories - static and dynamic RAMS; Pseudon-NMOS and dynamic PLA; Low power design and system level consideration.
Course learning outcomes
- Explain CMOS technology fabrication and device characteristics and parasitic effects
- Design digital logic gates and standard cells at transistor schematic and corresponding layouts level in CMOS technology using pseudo-nMOS, pass transistor, footed and footless domino logic families
- Explain and evaluate the effect of the parasitic and loading on CMOS circuit operation and performance in terms of size, area and noise margin and ways to minimise delay
- Model the effect of interconnect upon a design and to apply strategies to mitigate problems arising from interconnect loading
- Explain the function of CMOS memory circuits and design basic CMOS ROM and PLA circuits
- Explain factors that influence circuit reliability and be able to apply reasonable design margins
- Explain the effect of scaling on circuit behaviour and appreciate technology trends with respect to scaling
- Explain system level considerations such as floor planning, power dissipation, clock skew and micro-architecture to system performance
- Use a set of software tools to specify, synthesise, layout and simulate microelectronic circuits
- Demonstrate team work to design of a major digital system module